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MIRANDELA: "Millimeter-wave integration in Nanoelectronics for Modern Wireless 5 A Communications"
Funding agency: EC (European Commission) under the ENIAC 2009 grant n.120221.
Project members/Partners
STMicroelectronics (coordinator, France)
Austrian Center of Competence in Mechatronics – ACCM (Austria); Centre National de la Recherche Scientifique CNRS-IEMN (France); Danube Integrated Circuit Engineering DICE (Austria); EPFL (Switzerland); FOUNDATION FOR RESEARCH AND TECHNOLOGY HELLAS (Greece); Grenoble Institut National Polytechnique G-INP (France); IMS-L (France); INTEGRATED SYSTEMS DEVELOPMENT (United Kingdom); Institut Supérieur de l’Electronique et du Numérique (France); Commissariat a l’Energie Atomique CEA (France); POLITECNICO DI MILANO (Italy); Q-Free asa (Norway); STIFTELSEN SINTEF (Norway); ST-Ericsson (Belgium, Finland, France, Nederland, United Kingdom); STMicroelectronics (Italy); Aalto-korkeakoulusäätiö (Finland); Università degli Studi di Modena e ReggioEmilia (Italy); Università degli Studi di Pavia (Italy); UNIVERSITAT POLITECNICA DE CATALUNYA (Spain).
Project manager @ UniMORE: Luca Larcher
Start date: 01/05/2010
End date: 30/04/2013

The MIRANDELA project aims to the Millimetre-wave and Radio-frequency integration in Nanoelectronics CMOS Platforms for Modern Wireless 5 A Communications. Starting from core CMOS nodes, specific works will be conducted in order to offer a silicon technology and design platform adequate for the development of modern wireless communication applications. They can be “labelled” as 5A communications: Anything to be transferred from/to Anybody located Anywhere at Anytime using the most appropriate physical path from Any-path available between the sender and the recipient based on performance and/or economical considerations. Components available in core CMOS technology nodes as well as those made available by using specific process steps will be characterized, optimized and modelled in the RF and millimetre-wave range as well as for analog operation targeting very low power design of RF blocks and functions. The design solutions will be studied for reducing Time to Market and cost. Starting from the electrical models, efficient and cost/performance optimized design packages will be constructed. Moreover, specific flows and methods required for this kind of applications will be studied and applied for the design of RF and millimetre-wave building blocks. A significant effort will be devoted to the architecture of RF and millimetre-wave functions. In addition to traditional analog RF design, there are several new ideas that will be eventually deployed in such a technology node: millimetre-wave design in pure CMOS, RF design at very low power consumption, digital enhanced RF design, auto calibration of RF functions, Software Defined Radio (SDR), Cognitive Radio (CR), repairable functions, BIST introduction, etc. The capability of these technologies for making highly integrated communication mobile terminals on a single chip will be demonstrated. Demonstrators will be realized in the 45/40nm as well as the 32/28nm CMOS nodes by capitalizing on previous developments.